Test structure placement on a semiconductor wafer
US9349662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2012 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Dec 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.