Patent · US Active

Chip arrangement and method of manufacturing the same

US9349680B2 · kind B2 · utility

0Cited by

3References

19Claims

0Family size

Assignee

Infineon Technologies Austria AG · AT

Inventors

Joachim Mahler · Regensburg, DE
Peter Strobel · Regensburg, DE
Edward Fuergut · Nuremberg, DE

Key dates

Filing date	Jan 5, 2014
Grant date	May 24, 2016
Priority date	—
Expiry date	Jan 5, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1434
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip arrangement is provided which comprises a carrier; and at least two chips arranged over the carrier; wherein a continuous insulating layer is arranged between the at least two chips and between the carrier and at least one of the at least two chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.