Systems and methods to enhance passivation integrity
US9349688B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2015 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jul 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.