Semiconductor device with reduced via resistance
US9349691B2 · kind B2 · utility
15Cited by
21References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jul 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.