Conal E. Murray
88Patents
13h-index
99Co-inventors
83Inventor score
Filing activity: Apr 26, 2002 → Mar 30, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8399314B2 | p-FET with a strained nanowire channel and embedded SiGe source and drain stressors | Electricity | 35 | Active |
| US7166913B2 | Heat dissipation for heat generating element of semiconductor device and related method | Electricity | 34 | Expired |
| US7067902B2 | Building metal pillars in a chip for structure support | Electricity | 31 | Expired |
| US8492208B1 | Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process | Performing Operations; Transporting | 30 | Active |
| US8445892B2 | p-FET with a strained nanowire channel and embedded SiGe source and drain stressors | Electricity | 25 | Active |
| US6972209B2 | Stacked via-stud with improved reliability in copper metallurgy | Emerging Cross-Sectional Technologies | 18 | Expired |
| US7298639B2 | Reprogrammable electrical fuse | Electricity | 17 | Expired |
| US7282802B2 | Modified via bottom structure for reliability enhancement | Electricity | 16 | Expired |
| US8716695B2 | Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process | Performing Operations; Transporting | 16 | Active |
| US7491643B2 | Method and structure for reducing contact resistance between silicide contact and overlying metallization | Electricity | 16 | Active |
| US8198174B2 | Air channel interconnects for 3-D integration | Electricity | 15 | Active |
| US9349691B2 | Semiconductor device with reduced via resistance | Electricity | 15 | Active |
| US9748169B1 | Treating copper interconnects | Electricity | 15 | Active |
| US6787912B2 | Barrier material for copper structures | Electricity | 13 | Expired |
| US9431354B2 | Activating reactions in integrated circuits through electrical discharge | Electricity | 11 | Active |
| US7214548B2 | Apparatus and method for flattening a warped substrate | Electricity | 11 | Expired |
| US7923838B2 | Method and structure for reducing contact resistance between silicide contact and overlying metallization | Electricity | 10 | Active |
| US6812143B2 | Process of forming copper structures | Electricity | 10 | Expired |
| US7846834B2 | Interconnect structure and method for Cu/ultra low k integration | Electricity | 10 | Active |
| US8138603B2 | Redundancy design with electro-migration immunity | Electricity | 9 | Active |
| US7371684B2 | Process for preparing electronics structures using a sacrificial multilayer hardmask scheme | Electricity | 9 | Expired |
| US7260810B2 | Method of extracting properties of back end of line (BEOL) chip architecture | Physics | 8 | Expired |
| US9859157B1 | Method for forming improved liner layer and semiconductor device including the same | Electricity | 8 | Active |
| US7456098B2 | Building metal pillars in a chip for structure support | Electricity | 8 | Active |
| US7927895B1 | Varying capacitance voltage contrast structures to determine defect resistance | Electricity | 8 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.