Patent · US Active

Integrated WLUF and SOD process

US9349698B2 · kind B2 · utility

0Cited by

1References

11Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Rubayat Mahmud · Chandler, US
Saikumar Jayaraman · Chandler, US
Sriram Muthukumar · Chandler, US

Key dates

Filing date	Jun 27, 2012
Grant date	May 24, 2016
Priority date	—
Expiry date	Jun 27, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/351
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.