Semiconductor device and method of forming stress-reduced conductive joint structures
US9349700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Mar 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.