Semiconductor package stack structure having interposer substrate
US9349713B2 · kind B2 · utility
54Cited by
36References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2015 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.