Method for manufacturing graphene transistor based on self-aligning technology
US9349825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jul 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.