Field effect transistors and methods of forming same
US9349860B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Mar 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/512
Abstract
Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate, the substrate having a first source/drain feature and a second source/drain feature formed thereon. The semiconductor device further includes a first nanowire on the first source/drain feature and a second nanowire on the second source/drain feature, the first nanowire extending vertically from an upper surface of the first source/drain feature and the second nanowire extending vertically from an upper surface of the second source/drain feature. The semiconductor device further includes a third nanowire extending from an upper end of the first nanowire to an upper end of the second nanowire, wherein the first nanowire, the second nanowire and the third nanowire form a channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.