Method and apparatus for instruction scheduling using software pipelining
US9354850B2 · kind B2 · utility
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3References
11Claims
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Key dates
| Filing date | Oct 6, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Oct 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for scheduling loop processing of a reconfigurable processor includes generating a dependence graph of instructions for the loop processing; mapping a first register file of the reconfigurable processor on an arrow indicating inter-iteration dependence on the dependence graph; and searching for schedules of the instructions based on the mapping result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.