Won-Sub Kim
28Patents
6h-index
43Co-inventors
65Inventor score
Filing activity: Mar 31, 1999 → Dec 2, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6427223B1 | Method and apparatus for adaptive verification of circuit designs | Physics | 20 | Expired |
| US6449745B1 | Method and apparatus for random stimulus generation | Physics | 20 | Expired |
| US7900111B1 | Method and apparatus for random stimulus generation | Physics | 15 | Active |
| US6513144B1 | Method and apparatus for random stimulus generation | Emerging Cross-Sectional Technologies | 12 | Expired |
| US6553531B1 | Method and apparatus for random stimulus generation | Physics | 8 | Expired |
| US6493841B1 | Method and apparatus for determining expected values during circuit design verification | Physics | 6 | Expired |
| US9164769B2 | Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array | Physics | 4 | Active |
| US8555005B2 | Memory managing apparatus and method using a pointer indicator bit to perform garbage collection | Physics | 3 | Active |
| US8745608B2 | Scheduler of reconfigurable array, method of scheduling commands, and computing apparatus | Physics | 3 | Active |
| US6499127B1 | Method and apparatus for random stimulus generation | Physics | 3 | Expired |
| US8869129B2 | Apparatus and method for scheduling instruction | Physics | 2 | Active |
| US9411582B2 | Apparatus and method for processing invalid operation in prologue or epilogue of loop | Physics | 1 | Active |
| US9311270B2 | Scheduler and scheduling method for reconfigurable architecture | Physics | 1 | Active |
| US8930929B2 | Reconfigurable processor and method for processing a nested loop | Physics | 1 | Active |
| US10474574B2 | Method and apparatus for system resource management | Emerging Cross-Sectional Technologies | 1 | Active |
| US7063989B2 | Method of aligning a semiconductor substrate with a semiconductor alignment apparatus | Electricity | 1 | Expired |
| US9063735B2 | Reconfigurable processor and method for processing loop having memory dependency | Physics | 1 | Active |
| US9395962B2 | Apparatus and method for executing external operations in prologue or epilogue of a software-pipelined loop | Physics | 1 | Active |
| US9304967B2 | Reconfigurable processor using power gating, compiler and compiling method thereof | Emerging Cross-Sectional Technologies | 0 | Active |
| US9286074B2 | NOP instruction compressing apparatus and method in a VLIW machine | Physics | 0 | Active |
| US9971579B2 | Processor and command processing method performed by same | Physics | 0 | Active |
| US9354850B2 | Method and apparatus for instruction scheduling using software pipelining | Physics | 0 | Active |
| US10223269B2 | Method and apparatus for preventing bank conflict in memory | Physics | 0 | Active |
| US9383981B2 | Method and apparatus of instruction scheduling using software pipelining | Physics | 0 | Active |
| US9727528B2 | Reconfigurable processor with routing node frequency based on the number of routing nodes | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.