Mapping processing logic having data-parallel threads across processors
US9354944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2009 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Jul 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads into one or more workgroups, associating a first workgroup from the one or more workgroups with an operating system thread on the processor core, and configuring threads from the first workgroup as user-level threads within the operating system thread. In an example, a method enables the execution of GPU-kernels that has been previously configured for a GPU, to execute on a CPU such as a multi-core CPU. The mapping of the numerous data-parallel threads to the CPU is done in such a manner as to reduce the number of costly operating system threads instantiated on the CPU, and to enable efficient debugging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.