Managing a translation lookaside buffer
US9355042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Dec 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing a translation lookaside buffer (TLB) at hardware in a virtualization enabled system. According to embodiments of the present invention, a series of operations caused by TLB miss would not need intervening from the hypervisor. On the contrary, when a TLB miss occurs, the hardware directly issues an interrupt to a virtual machine. In this way, the TLB can be efficiently managed by means of a hardware-level auxiliary translation table. Therefore, system overheads can be greatly reduced and system performance can be improved. Methods and apparatuses associated with hardware, hypervisor, and virtual machine in a virtualization enabled system are disclosed, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.