Method and apparatus for camouflaging a standard cell based integrated circuit
US9355199B2 · kind B2 · utility
0Cited by
37References
25Claims
0Family size
Inventors
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Sep 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logic cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.