Non-volatile memory and method of operating the same
US9355725B2 · kind B2 · utility
3Cited by
13References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.