Method of manufacturing semiconductor device
US9355858B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Feb 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.