Cooling channels in 3DIC stacks
US9355933B2 · kind B2 · utility
9Cited by
33References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Feb 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.