Bump structures for semiconductor package
US9355977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Mar 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.