Embedded SONOS based memory cells
US9356035B2 · kind B2 · utility
3Cited by
23References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.