3-D nonvolatile memory device and method of manufacturing the same
US9356041B2 · kind B2 · utility
2Cited by
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7Claims
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Key dates
| Filing date | Dec 12, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Dec 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.