Systems and methods involving phase detection with adaptive locking/detection features
US9356611B1 · kind B1 · utility
29Cited by
28References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Jan 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.