Clock multiplexer for generating glitch-free clock signal
US9360883B1 · kind B1 · utility
8Cited by
19References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 26, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Aug 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fully digital glitch-free clock multiplexer includes a monitoring circuit that automatically switches to a newly selected clock, after a defined time period, from a currently selected clock, when the currently selected clock is absent. A maximum time limit is calculated based on a min and max clock frequency ratio. The monitoring circuit operates only when the clock is being switched. This provides flexibility to software to switch the clock any time whether or not the current clock is present, and prevents the system from hanging in the absence of the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.