Apparatus and method for low-latency invocation of accelerators
US9361116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.