Runtime chargeback in a simultaneous multithreading (SMT) environment
US9361159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Jul 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for chargeback with simultaneous multithreading (SMT) by a computer is provided. One or more of an operating system and a second-level hypervisor of the computer manage a logical core configuration for simultaneous multithreading, the operating system and/or the second-level hypervisor has control over a logical core and control over logical threads on the logical core. The operating system and/or the second-level hypervisor is configures a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core. The logical core is run on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core. A capacity use time is determined for each of the logical threads executing on the physical threads of the single physical core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.