Patent · US Active

Splitable and scalable normalizer for vector data

US9361268B2 · kind B2 · utility

0Cited by

6References

5Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Maarten J. Boersma · Holzgerlingen, DE
Markus Kaltenbach · Holzgerlingen, DE
Christophe J. Layer · Eppelheim, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Jan 9, 2014
Grant date	Jun 7, 2016
Priority date	—
Expiry date	Oct 12, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F2207/382
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.