Memory device, memory system and operating method thereof
US9361954B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Dec 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a cell array having a plurality of word lines, an address counting unit suitable for generating a counting address that is changed whenever one or more of the plurality of word lines are refreshed, and a control unit suitable for selecting a word line corresponding to the counting address among the plurality of word lines and refreshing the selected word line within a first period in response to a refresh command during a first operation mode, within a second period that is longer than the first period during a second operation mode, and within a third period that is shorter than the second period in a high frequency section after the second operation mode begins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.