Method of increasing read current window in non-volatile memory
US9361994B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure is provided including an array of non-volatile memory (NVM) cells arranged in rows and columns, each cell including a NVM transistor having a body bias terminal coupled to body bias supply. The memory structure further includes a control system to control the body bias supply to adjust a body bias voltage coupled to the body bias terminals during read operations of the memory structure to compensate for shifts in threshold voltages (VTH) of the NVM transistors to maintain a read current window (IRCW) between a cell in which the NVM transistor is ON and a sum of leakage current through cells in which the NVM transistor is OFF. Methods of operating the memory structure are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.