Flash memory system using complementary voltage supplies
US9361995B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Jan 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.