Memory device using soft and hard repair operations and memory system including the same
US9362008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Dec 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit that generates a soft repair signal, a selection information generation circuit that generates first selection information by using first bits of a latched address latched by the address latch circuit, first to Nth register circuits that store second bits of the latched address as repair data by being selected by the first selection information when the soft repair signal is activated, and first to Nth memory blocks that perform repair operations using the repair data stored in the respective first to Nth register circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.