Semiconductor process
US9362125B2 · kind B2 · utility
2Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Sep 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
Abstract
A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.