Three-dimensional (3D) semiconductor devices and methods of fabricating 3D semiconductor devices
US9362226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Mar 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.