Clock generator circuit
US9362894B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | May 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator includes a diagnostic circuit that includes first and second muxes, first and second comparators, a logic gate, and a counter. The first mux receives first and second voltage signals and outputs a first intermediate signal based on a control signal. The second mux receives third and fourth voltage signals and outputs a second intermediate signal based on the control signal. The first and second comparators compare the intermediate signals with a first signal that is indicative of a DC value of the clock signal for generating first and second comparison signals. The logic gate receives the first and second intermediate signals and generates a control signal. The counter receives the clock signal and the control signal and generates a clock ready signal that is indicative of stability and quality of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.