Patent · US Active

Efficient error correction of multi-bit errors

US9362953B2 · kind B2 · utility

5Cited by

0References

18Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Kern · Munich, DE
Michael Goessel · Roter Dudel, DE
Christian Badack · Heinsberg, DE

Key dates

Filing date	Aug 2, 2013
Grant date	Jun 7, 2016
Priority date	—
Expiry date	Apr 29, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/6575
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·α3j+Zw2·α2j+Zw1·αj+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)≠(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value Δvi= for the bit position i may then be determined on the basis of the error correction expression evaluated for αj.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.