Loop streaming detector for standard and complex instruction types
US9367317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Dec 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is configured to receive a first instruction, decode the first instruction into an entry point vector to a first microcode flow in the microcode storage, the entry point vector comprising a first indicator specifying a number of clock cycles associated with the first microcode flow, initiate the microcode storage, wherein the microcode storage inserts microinstructions of the first microcode flow into an instruction queue, count clock cycles after initiating the microcode storage, and decode a second instruction without first receiving a return from the microcode storage, wherein the second instruction is decoded at a particular clock cycle based on the number of clock cycles associated with the first microcode flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.