Doubling thread resources in a processor
US9367318B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are provided for managing thread execution in a processor. Multiple instructions are fetched from fetch queues. The instructions satisfy the condition that they involve fewer bits than the integer processing pathway that is used to execute them. The instructions are decoded, and divided into groups. The instructions are processed simultaneously through the pathway, such that part of the pathway is used to execute one group of instructions and another part of the pathway is used to execute another group of instructions. These parts are isolated from one another so the execution of the instructions can share the pathway and execute simultaneously and independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.