James Laudon
25Patents
12h-index
27Co-inventors
81Inventor score
Filing activity: May 5, 1995 → Dec 22, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8762951B1 | Apparatus and method for profiling system events in a fine grain multi-threaded multi-core processor | Physics | 177 | Active |
| US6049476A | High memory capacity DIMM with data and state memory | Physics | 126 | Expired |
| US5680576A | Directory-based coherence protocol allowing efficient dropping of clean-exclusive data | Physics | 85 | Expired |
| US5727150A | Apparatus and method for page migration in a non-uniform memory access (NUMA) system | Physics | 79 | Expired |
| US5790447A | High-memory capacity DIMM with data and state memory | Physics | 73 | Expired |
| US5686730A | Dimm pair with data memory and state memory | Physics | 43 | Expired |
| US6182195A | System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer | Physics | 32 | Expired |
| US5787476A | System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer | Physics | 30 | Expired |
| US7454631B1 | Method and apparatus for controlling power consumption in multiprocessor chip | Emerging Cross-Sectional Technologies | 26 | Expired |
| US5634110A | Cache coherency using flexible directory bit vectors | Physics | 25 | Expired |
| US9207944B1 | Doubling thread resources in a processor | Physics | 14 | Active |
| US5991895A | System and method for multiprocessor partitioning to support high availability | Physics | 12 | Expired |
| US10875682B1 | Auxiliary gripping member | Performing Operations; Transporting | 3 | Active |
| US9384036B1 | Low latency thread context caching | Physics | 3 | Active |
| US7574566B2 | System and method for efficient software cache coherence | Physics | 1 | Active |
| US7281096B1 | System and method for block write to memory | Emerging Cross-Sectional Technologies | 0 | Expired |
| US8195903B2 | System and method for metering requests to memory | Emerging Cross-Sectional Technologies | 0 | Active |
| US11556690B2 | Generating integrated circuit placements using neural networks | Physics | 0 | Active |
| US12248745B2 | Generating integrated circuit placements using neural networks | Physics | 0 | Active |
| US11216609B2 | Generating integrated circuit placements using neural networks | Physics | 0 | Active |
| US11853677B2 | Generating integrated circuit placements using neural networks | Physics | 0 | Active |
| US10127076B1 | Low latency thread context caching | Physics | 0 | Active |
| US9367318B1 | Doubling thread resources in a processor | Physics | 0 | Active |
| US9218310B2 | Shared input/output (I/O) unit | Physics | 0 | Active |
| US10850297B1 | Wide-body roller paint system | Performing Operations; Transporting | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.