Error correction operations in a memory device
US9367391B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Jul 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices configured to determine if an error exists in read data and to respond to determined errors, as well as methods of operating such memory devices. In at least one embodiment, an internal controller of a memory device periodically performs internal error correction operations on stored user data and corrects user data in the memory device independently from instructions from an external memory access device. In further memory devices, an internal controller performs internal error correction operations on stored user data and adjusts trim values that define voltages to be utilized during a read operation in response to determining that the read user data comprises an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.