NAND flash memory having internal ECC processing and method of operation thereof
US9367392B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Oct 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.