Nonvolatile memory cell structure with assistant gate
US9368161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/64
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first oxide define (OD) region and a second oxide define (OD) region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.