Hardware chip select training for memory using write leveling mechanism
US9368169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2012 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Dec 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.