Read strobe gating mechanism
US9368172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Dec 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory controller includes a communication port that receives a timing reference signal for reading data from a memory device. A control circuit generates a gating signal indicative of a read window. A gating adjustment circuit generates an adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal. A gating circuit generates a first gated timing reference signal for reading data by gating a delayed version of the timing reference signal with the adjusted gating signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.