Set and reset operation in phase change memory and associated techniques and configurations
US9368205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Mar 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.