Semiconductor devices including a capping layer and methods of forming semiconductor devices including a capping layer
US9368362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2014 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | May 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.