Method for manufacturing a semiconductor device
US9368403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2015 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.