Package substrate with testing pads on fine pitch traces
US9370097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (μm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.