Testing of semiconductor chips with microbumps
US9372206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2015 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Aug 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16238
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.