Inter-chip interconnect protocol for a multi-chip system
US9372800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | May 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.