Apparatus to reduce retention failure in complementary resistive memory
US9373395B1 · kind B1 · utility
7Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2015 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Mar 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.