Chip on package structure and method
US9373527B2 · kind B2 · utility
43Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2014 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Jul 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.